1. Field of the Invention
This invention relates to methods of manufacturing field-effect semiconductor devices and more particularly to a method of providing self-aligned polysilicon gate IGFET devices having low leakage, shallow junction source/drain regions by the use of ion implantation and diffusion techniques.
2. Description of the Prior Art
Traditionally, n-channel IGFET source/drain junctions have been formed by thermal diffusion from chemical sources such as doped oxides. Advances in semiconductor processing have led to the introduction of such features as recessed oxide isolation, for example see the article, "Selective Oxidation of Silicon and its Device Applications," E. Kooi et al., Semiconductor Silicon 1973, Electrochemical Society, pp. 860-879. More recent trends have led to smaller horizontal device geometries which also require scaling of vertical geometries as well. The article, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," R. H. Dennard et al., IEEE J. Solid-State Circuits, Vol. SC-9, No. 5, October 1974, pp. 256-267, describes some of the design criteria necessary to achieve device scaling. Because of the requirement for low resistivity, shallow source/drain regions the use of conventional thermal diffusion becomes unacceptable. Ion-implantation, with its ability to provide controlled quantity and location of dopant atoms, has become the acceptable choice for providing junction regions in scaled down devices. Dennard et al. suggest the direct ion implant of dopant through a thin gate oxide to form source/drain regions. U.S. Pat. No. 4,160,987 (Dennard et al.) describes a more detailed fabrication process in which self-aligned source/drain regions are formed by ion implanting arsenic at about 100 KeV energy and 4.times.10.sup.15 ions/cm.sup.2 dosage. [Designation of exponential powers of ten will hereinafter be expressed for example as: 4E15 dose.] The arsenic is implanted conveniently through a gate oxide layer and thereafter subjected to a thermal oxidation process at about 1000.degree. C. to grow a silicon dioxide junction passivating layer of between 1500 and 5000 Angstroms. This process electrically activates the implanted ions and provides for some diffusion into the silicon substrate. A variation in this post implant process is taught in U.S. Pat. No. 4,170,492 (Bartlett et al.) in which a lower temperature, non-annealing oxidizing step is used to enhance the growth of oxide over implanted regions.
Because ion implantation is a damage-producing technique due to the physical impact of energetic ions, thermal annealing of implanted cyrstalline silicon is critically important to providing good electrical characteristics of finished devices. Many processes, like that of Bartlett, above, may provide insufficient annealing. Any remaining, or residual, implant damage when made electrically active can enhance the reverse bias junction leakage current if the damage lies hear the junction depletion regions.
Many references are available which relate to processing techniques for reducing ion implantation caused damage. For example, the article, "Adaption of Ion Implantation for Integrated Circuits," S. Prussin et al., Extended Abstracts, Vol. 74-1, Spring Meeting of the Electrochemical Society, May 12-17, 1974, Abstract 85, pp. 213-5, emphasizes the importance of a non-oxidizing thermal annealing step following the ion implant of phosphorus in order to provide low leakage junctions. E. H. Bogardus et al. in the article, "Removal of Implant Damage," IBM Technical Disclosure Bulletin, Vol. 18, No. 10, March 1976, p. 3301, suggests that a mildly oxidizing atmosphere be used to provide low leakage arsenic implanted junction formed with the use of a screen oxide.
While the use of a screen oxide is advantageous from a processing point of view, as it protects against the introduction of undesirable impurities, W. K. Tice et al. in their paper, "The Isochronal Annealing Behavior of Silicon Implanted with Arsenic Ions," Abstract No. 334, Extended Abstracts Vol. 76-2, Fall Meeting of The Electrochemical Society, October 17-22, 1976, pp. 863-4, reported that thermal annealing of arsenic implanted at 150 KeV with a dose of 8E15 through a 200 Angstrom screen oxide showed deep-lying dislocation defects after thirty minutes anneal in a non-oxidizing atmosphere at 1100.degree. C. Yet, R. Varma et al. in their paper, "Abrupt Junctions by Ion-Implantation Doping of Silicon and Monitoring Damage-Annealing by Laser Raman Scattering," Abstract No. 112, Extended Abstracts, Vol. 79-1, Spring Meeting of the Electrochemical Society, May 6-11, 1979, pp. 310-313, reported that the presence of a screen oxide prevents non-annealable damage when ion implant of arsenic was followed by nitrogen annealing at temperatures between 558.degree. and 704.degree. C., temperatures at which little thermal diffusion occurs. The recent paper by Wada et al, "Arsenic Ion Implanted Shallow Junction," J. Electrochemical Society, Vol. 127, No. 2, February 1980, pp. 461-6, further examines the non-oxidizing annealing of arsenic ion implanted through a screen oxide to provide shallow junctions of less than one micron and found that, although knock-on oxygen provided a source for non-annealable crystalline defects, adequate thermal annealing with its inherent diffusion of impurity enables the containment of defects within the dopant profile.
While all of the above references relate primarily to the formation of ion-implanted junctions with little or no movement of the as-implanted dopant profile, other techniques in which the ion-implanted region is used primarily as a pre-diffusion source are also known. For example, H. Muller et al., in their article, "Influence of an Oxidizing Annealing Ambient on the distribution of As, Sb, and Ga Implanted into Silicon," J. Electrochemical Society, Vol. 122, No. 9, September 1975, pp. 1234-8, describe the effects of an oxidizing anneal on arsenic implanted into bare silicon and show that as the silicon surface is oxidized the implanted arsenic is pushed ahead of the oxidation front. Experiments were carried out by wet oxygen and steam annealing and demonstrated that little or no alteration of the arsenic concentration profile occurs between the temperatures of 850.degree. and 1000.degree. C. However, when the oxidation step was followed by annealing in nitrogen for 20 minutes at 1000.degree. C. substantial diffusion of the arsenic occured.
In attempting to utilize ion implantation techniques to fabricate integrated circuit MOSFET devices we initially chose to use a technique similar to that described by the above Dennard et al. references. That is we chose to use the MOSFET gate oxide as a screen through which a high dose of arsenic was implanted. This was followed by an oxidation process to provide silicon surface and polysilicon gate passivation and to allow the implanted arsenic to diffuse to a junction depth of about one-half a micron. As recently reported by W. R. Hunter et al., IEEE TR. Electron Devices, Vol. EO-26, No. 4, April 1979, pp. 353-9, we found that thick oxide parasitic device threshold voltages were unsatisfactory due to the apparent field provided by trapped holes present in the semi-recessed field oxide regions. Since the source/drain arsenic implants were carried out without a blocking mask other then that of the field oxide and the polysilicon gate electrodes, the cause of the trapped charge was attributed to the presence of arsenic in the upper portion of the field oxide. Our initial attempt to remove the implant-caused charges was to increase the initial thickness of the field oxide and then to etch away the arsenic containing oxide, see the article "Low Leakage Implanted Source," H. J. Geipel and R. B. Shasteen, IBM Technical Disclosure Bulletin, Vol. 18, No. 2 July 1975, p. 337. Although this technique eliminated the arsenic from the field oxide regions it also removed the protective screen oxide as well. In addition, when used with the semi-recessed oxide isolation scheme of Kooi et al, the etching also increased the areas of the diffused regions, attacked the thermal oxide on previously oxidized first level polysilicon and undercut the gate oxide of self-aligned polysilicon gate devices, all of which are extremely important areas of device design sensitivity. Hunter et al. used a two-step etching process which involved removal of the screen oxide and a portion of the arsenic contaminated field oxide, followed by growth of thin thermal oxide over the implanted regions and a second etching step to remove more of the arsenic contaminated field oxide. Although this etchback technique was effective in raising the thick isolation oxide threshold voltage by a factor of 2, the additional process steps required are undesirable in a semiconductor process in which each additional step decreases product yield.